The present invention relates to a semiconductor integrated circuit device, and more particularly to effective technology to be applied to a semiconductor integrated circuit device having a dynamic type random access memory and a non-volatile memory.
A semiconductor integrated circuit device containing a microcomputer has a RAM (Random Access Memory) and a ROM (Read Only Memory) as a storage unit of the microcomputer. A S (Static) RAM is installed as a RAM, and its memory cell (storage element) is composed of six MOSFETs (six-MOS structure). A mask ROM, an EP (Erasable Programmable) ROM or an EEP (Electrically Erasable Programmable) ROM is installed as a ROM. A memory cell of FLOTOX (Floating Gate Tunnel Oxide) structure is used as an EEPROM.
In the semiconductor integrated circuit device of such constitution, since the memory cell of the SRAM used as a RAM is constituted in the six-MOS structure, the memory cell area is increased and the integration degree is decreased. Therefore, it has been proposed to use a D (Dynamic) RAM as a RAM of such semiconductor integrated circuit device in place of the SRAM. For example, refer to "Nikkei Microdevice" published by Nikkei MacGraw Hill on July 1987, pp 71-73. The DRAM in the proposed semiconductor integrated circuit device is composed of series circuit of a memory selecting MOSFET and an information storing capacitance element. The information storing capacitance element is composed of n type semiconductor region (lower electrode) formed on main surface portion of a semiconductor substrate, a dielectric film and a plate electrode (upper electrode) respectively stacked in sequence, i.e., in so-called planer structure.
In this semiconductor integrated circuit device, since the element number of the memory cell of the DRAM is little, it is characterized in that the memory cell area can be decreased and the integration degree can be improved.
Also in the semiconductor integrated circuit device, since the memory cell of the DRAM is formed utilizing a part of the manufacturing process of the FLOTOX structure of the EEPROM, it is characterized in that the manufacturing process can be reduced. In the semiconductor integrated circuit device as above described, the MISFET to constitute the DRAM, the EEPROM and the peripheral circuit is installed, and the manufacturing method of these elements is as follows.
First, in the floating gate electrode forming region of the memory cell of the FLOTOX structure of the EEPROM, a gate insulation film is formed on the main surface portion of the semiconductor substrate.
Second, a part of the gate insulation film is removed, and a tunnel silicon oxide film having film thickness less than that of the gate insulation film is formed.
Third, a floating gate electrode is formed on the gate insulation film and the tunnel silicon oxide film.
Fourth, a gate insulation film is formed on the floating gate electrode. Utilizing this process, according to the same manufacturing process as this process, a dielectric film (silicon oxide film) of the information storing capacitance element of the memory cell of the DRAM and a gate insulation film of the MISFET of the peripheral circuit are formed.
Fifth, a gate insulation film is interposed on the floating gate electrode of the memory cell of the FLOTOX structure, and a control gate electrode is formed. Utilizing this process, according to the same manufacturing process as this process, a plate electrode (upper electrode) is formed on the dielectric film of the information storing capacitance element of the memory cell of the DRAM and a gate electrode is formed on the gate insulation film of the MISFET of the peripheral circuit.